Semiconductor packages have been continuously required to be thinned and lightened in terms of a shape, and have been required to be implemented in a system in package (SiP) form requiring complexation and multi-functionality in terms of a function. In accordance with such a development trend, a fan-out wafer level package (FOWLP) has been recently prominent, and attempts to satisfy requirements of semiconductor packaging by applying several techniques to the FOWLP have been conducted. Particularly, in accordance with the approach of commercialization of 5G mobile communications and Internet of things (IoT), it is required to process data that are explosively increased and perform communications between semiconductors or between devices in a radio frequency region. To this end, in all boards such as a semiconductor, a semiconductor package, a mainboard, and the like, it has been demanded to implement circuits having a finer pitch, more excellent signal transfer characteristics, and higher reliability as compared to existing cases.
Meanwhile, as existing circuit line widths and circuit pitches gradually become finer, surfaces of an insulating material and a metal circuit need to be smooth without substantially having a surface roughness. However, in this case, physical coupling force due to the surface roughness hardly exists, such that close adhesion between respective layers or between an insulating material and a metal circuit is decreased to cause a defect such as delamination. In addition, a photoimagable dielectric (PID) mainly used in a fan-out wafer level package (FOWLP) requires heat treatment at a high temperature in a process to promote oxidation of a copper circuit mainly used as the metal circuit, resulting in a reduction in close adhesion between the PID and the copper circuit.